Radar / AI infrastructure / openTPU
openTPU: an open-source AI accelerator designed by AI agents
Full AI-accelerator stack (SystemVerilog RTL, ISA, bit-exact simulator, compiler, profiler) built by AI agents, running Qwen3 and LFM2.5 on a Kintex-7 FPGA PCIe card.
Why it matters
The first end-to-end open-source chip whose hardware was designed by AI agents — a live experiment on how far agents can go in silicon, and a learnable monorepo of accelerator architecture.
What you could build with it
A hardware startup could fork openTPU as a reference design to prototype a domain-specific inference card for its own models, shipping an FPGA-based demo appliance before committing to an ASIC tapeout. A university course could use the monorepo to teach the full matmul-to-wires stack, with students running the simulator instead of needing fab access.
Does it hold up?
Early but tangible: the README shows LFM2.5-230M chatting on a real Kintex-7 PCIe card with hardware utilization monitoring, though the maintainers honestly flag simulation-first performance estimates — prototype-grade throughput, not a production accelerator yet.
Built with openTPU
- HN front-page discussion: AI is now capable of developing its own inference hardwareHN · Front-page thread with 90+ points and hundreds of comments debating the agent-designed hardware claims.
- AI Is Learning to Build the Hardware It Runs OnMedium · Developer essay on the openTPU project and what AI-designed accelerators mean for software engineers.
- fesens/auto-arch-tournamentgithub · Predecessor project from the same author: an LLM-driven agent loop that iteratively proposes and grades RISC-V microarchitecture improvements; openTPU applies those agent-driven design lessons to AI accelerators.
Learn more
First spotted on github: source.
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