Qwenputer: a functioning, deterministic RISC-V CPU compiled into Qwen3.5's weights
An experimental model with a 32-bit RISC-V CPU compiled into Qwen3.5-4B's weights, using Gated DeltaNet layers as RAM to run C and MicroPython inside forward passes with no external runtime, passing riscv-tests.
Why it matters
The model itself becomes the computer — exact arithmetic (97.5 vs 55.0 on DeepMind's mul_big) without a tool call or sandbox — a genuinely new architecture direction built on a Chinese base model.
What you could build with it
A computer-architecture lecturer could use the model to teach how a CPU executes instructions, letting students watch arithmetic run inside model weights instead of a separate simulator.
Does it hold up?
A working research demo, not a product: it passes riscv-tests and ships code and weights, but runs at roughly 3,200 trace tokens per second on an L4 and exists to prove an architecture idea.
Built with Qwenputer
- Qwenputer compiles a RISC-V CPU into Qwen3.5-4B weightsblog · Coverage of the arithmetic gains, the 230,000-position verification replay, and the follow-up work on hidden reasoning.
- A developer compiled a working RISC-V CPU into a 4B parameter model's weightsblog · Explainer on how compiler-generated weights turn logic gates into linear algebra the model runs during inference.
- What is Qwenputer? A Working RISC-V CPU Inside Qwen3.5medium · Walkthrough of the CPU-in-weights design, the ADDR/VAL/STEP trace tokens, and the RvChat driver.
- divagr18/qwenputergithub · Official code, weights compiler and RvChat driver for the in-weights CPU.
Learn more
First spotted on github: source.
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